Synchronous delay based UWB pulse generator in FPGA

Punithavathi Duraiswamy; Xiao Li; Johan Bauwelinck; Jan Vandewege; Peter Vaes; Stephanie Teughels

doi:10.1587/elex.9.868

IEICE Electronics Express

Online ISSN : 1349-2543
ISSN-L : 1349-2543

Synchronous delay based UWB pulse generator in FPGA

Punithavathi Duraiswamy, Xiao Li, Johan Bauwelinck, Jan Vandewege, Peter Vaes, Stephanie Teughels

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Keywords: UWB, transmitters, pulse generator, synchronous delay, FPGA

JOURNAL FREE ACCESS

2012 Volume 9 Issue 9 Pages 868-873

DOI https://doi.org/10.1587/elex.9.868

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Abstract

This paper presents an architecture for generating UWB pulses with a high centre frequency accuracy. The architecture allows to generate frequencies twice that of the FPGA clock using synchronous delays and is implementable in all types of FPGA. With a FPGA clock of 150MHz, we generate RF pulse of 300MHz with a maximum fractional bandwidth of 30%. The architecture also allows pulse width increment in steps of the clock period.

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