For ultra-high-density integration of gate-controlled quantum devices, one possible phenomenon limiting the ultimate integration density is a side-gating effect which has not been properly addressed so far for nanodevices. The purpose of this paper is to attempt to remove the side-gating effect from the GaAs quantum wire transistors where we recently have found presence of anomalously large side-gating effect. We first present data on the side-gating and we explain its mechanism in terms of tunneling injection of electrons by field concentration at gate edges caused by Fermi level pinning. Then, we apply our Si interface control layer (Si ICL) passivation process to reduce the pinning. By applying the Si ICL technique via thin GaAs cap layer, the anomalously large side-gating was completely suppressed, and only electrostatic side-gating theoretically expected from the device structure remained. [DOI: 10.1380/ejssnt.2005.332]