A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin

Koh Johguchi; Yuya Mukuda; Ken-ichi Aoyama; Hans Jürgen Mattausch; Tetsushi Koide

doi:10.1587/elex.4.21

LETTER

A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin

Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide

Author information

Keywords: SRAM, multi-port memory, distributed crossbar, multi-stage sensing

JOURNAL FREE ACCESS

2007 Volume 4 Issue 2 Pages 21-25

DOI https://doi.org/10.1587/elex.4.21

Details

Abstract

A 90nm CMOS, 64Kbit, 1.16GHz, 16 port SRAM with multi-bank architecture realizing 590Gbps random access bandwidth, 41mW power dissipation at 1GHz and 0.91mm² (13.9µm²/bit) area consumption is reported. Compared to conventional 16 port SRAM data, area and power consumption are reduced by factors 16 and 5, respectively, while maximum clock frequency is about a factor 2 higher.

Corresponding author

Register with J-STAGE for free!