2007 Volume 4 Issue 9 Pages 306-311
A low power high performance level converter circuit is presented. The performance and the robustness of this level converter are compared to those of the previous level converters using HSPICE simulations in a 65nm standard CMOS technology. The results of the comparison with the previously proposed circuits show 63%, 33%, 35%, and 8% reduction in the average power, the static power, the delay, and the area, respectively.