A new topology to design low-phase-noise low-power quadrature voltage-controlled-oscillator (QVCO) is proposed. The proposed topology is based on using a dynamic transistor biasing scheme in a typical voltage-controlled-oscillator (VCO). This method modifies the equivalent impulse-sensitivity-function (ISF) of oscillator to reduce the oscillator sensitivity to noise sources and as a result reducing the oscillator phase noise. A 1.8GHz, 1.8v designed QVCO with 0.18u CMOS technology based on the proposed topology shows a phase noise of -134dBc/Hz at 1MHz offset frequency from the carrier.