IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Operation scheduling for the synthesis of false loop free circuits
Shih-Hsu HuangChun-Hua Cheng
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JOURNAL FREE ACCESS

2007 Volume 4 Issue 14 Pages 448-454

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Abstract

If resource constraints are specified, the false loop free circuit must be built during the scheduling phase. Although the previous approach guarantees to have a false loop free circuit mapping, it does not attempt to minimize the number of control steps. In this paper, we present an effective approach to find a scheduled code, which not only guarantees to have a false loop free circuit mapping but also to minimize the number of control steps. Experimental results show that our approach achieves good results in terms of the number of control steps.

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© 2007 by The Institute of Electronics, Information and Communication Engineers
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