IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit
Kenichi OhhataKosuke YayamaYuichiro ShimizuKiichi Yamashita
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2007 Volume 4 Issue 22 Pages 701-706

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Abstract

This paper describes a high-speed CMOS track-and-hold (T/H) circuit with low distortion. We propose a T/H circuit with a body-bias control circuit to reduce distortion. This control circuit maintains a constant body bias for a switching MOS transistor in tracking mode. This reduces the variation in the threshold voltage due to the body-bias effect, thereby resulting in low distortion. The test chip fabricated using 90-nm CMOS technology shows a high SFDR of 56.3dB at a sampling frequency of 1GHz.

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© 2007 by The Institute of Electronics, Information and Communication Engineers
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