This paper presents a novel design-for-testability technique to reliably detect stuck-open faults in CMOS complex gates. The modified design uses an additional pair of transistors to establish a constant saturation current I_DDQ through the transistors under test. Variations in current level are monitored using a built-in current sensor to detect the presence of stuck-open faults. Circuit simulations verify that the proposed design is also resilient to time skews caused by unequal delays in circuit paths.