IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Standby power reduction using optimal supply voltage and body-bias voltage
Kyung Ki KimYong-Bin Kim
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JOURNAL FREE ACCESS

2008 Volume 5 Issue 15 Pages 556-561

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Abstract

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32nm CMOS technology comparing to the case where the method is not applied.

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© 2008 by The Institute of Electronics, Information and Communication Engineers
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