This letter presents a high-speed 8B/10B encoder design using a simplified coding table. The proposed encoder also includes a modified disparity control block. Logic simulation and synthesis have been done for the performance verification. After synthesized with a CMOS 0.18µm process, the proposed design shows the operating frequency of 343MHz with no latency. The synthesized chip area is 1886µm² with 189 logic gates. The proposed 8B/10B encoder shows the overall performance improvement compared to previous approaches.