IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A hybrid SA-EA method for finding the maximum number of switching gates in a combinational circuit
Ichiro Ruiz Obregon, Alberto Palacios Pawlovsky
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Keywords: combinational circuits, CMOS, switching gates, simulated annealing, evolutionary algorithms
JOURNAL FREE ACCESS

2008 Volume 5 Issue 18 Pages 756-761

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Abstract

This paper presents a hybrid of simulating annealing (SA) and an evolutionary algorithm (EA) to determine the input pair that cause the maximum number of switching gates in a combinational circuit. We found that this combination provides better results than those obtained when only using either SA or EA.

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© 2008 by The Institute of Electronics, Information and Communication Engineers
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