A 1-bit full adder cell based on majority function is designed and simulated. In this design the time consuming XOR gates are eliminated. Low-power consumption is targeted in implementation of our design. The circuit being studied is optimized for energy efficiency at 0.18-µm CMOS process technology. The new circuit has been compared to the previous work based on power consumption, speed and power delay product (PDP). HSPICE and Cadence simulations show that the proposed adder can work more reliably at different range of supply voltage. The proposed design has the best PDP in comparison with the others.