This paper describes a low-voltage design for a pipelined ADC that can operate in a 2.0-V_pp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output ranges of all MDACs by 50% compared to the ADC's input. We designed a 10-b pipelined ADC with the proposed front-end MDAC using a 90-nm CMOS process. The ADC achieved 2.0-V_pp rail-to-rail operation at only a 1-V supply and a 57.5-dB SNDR with only 3.4mW at 30MS/s despite using conventional folded-cascode op-amps.