Physical design challenges to nano-CMOS circuits

Kazuya Masu; Noboru Ishihara; Noriaki Nakayama; Takashi Sato; Shuhei Amakawa

doi:10.1587/elex.6.703

INVITED PAPER

Physical design challenges to nano-CMOS circuits

Kazuya Masu, Noboru Ishihara, Noriaki Nakayama, Takashi Sato, Shuhei Amakawa

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Keywords: CMOS, scaling, RF CMOS, interconnect integration, integration of diverse functionalities

JOURNAL FREE ACCESS

2009 Volume 6 Issue 11 Pages 703-720

DOI https://doi.org/10.1587/elex.6.703

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Abstract

There are many challenges inherent in the design of nano-CMOS. This paper describes our recent work relating to the physical design of CMOS circuits. First, in line with variation-aware design, a novel ingenious method of measuring variations in subthreshold characteristics is described. Next, recent RF CMOS issues and approaches to nano-CMOS are discussed. Finally, an on-chip transmission line interconnect developed for global wiring is discussed.

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