A12b, 40-MS/s, 4.1mW fully differential CBSC pipelined ADC in 0.18µm CMOS

Majid Zamani; Shahin Jafarabadi-Ashtiani; Masoud Dousti; Mohammad Naser-Moghadasi

doi:10.1587/elex.7.1714

LETTER

A12b, 40-MS/s, 4.1mW fully differential CBSC pipelined ADC in 0.18µm CMOS

Majid Zamani, Shahin Jafarabadi-Ashtiani, Masoud Dousti, Mohammad Naser-Moghadasi

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Keywords: CBSC, fully differential architecture, pipeline ADC, low-power design, preset levels designing, offset regulating

JOURNAL FREE ACCESS

2010 Volume 7 Issue 23 Pages 1714-1720

DOI https://doi.org/10.1587/elex.7.1714

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Abstract

In this paper a fully differential comparator-based switched-capacitor (CBSC) pipelined ADC is presented. For better performance and accuracy, we modified the differential architecture and introduced some practical issues on preset levels designing. For comparison, we used a simple comparator which can compensate offset easily. Finally we designed a 12b 40MS/s Fully Differential CBSC Pipelined ADC with proposed architecture in a 0.18-µm standard CMOS process. It achieves 75.2-dB spurious-free-dynamic range (SFDR) and 69.78-dB SNDR. In addition it consumes 4.1mW from a 1.8-V power supply at 40MS/s, which obtains a figure of merit of 460fJ/step.

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