LETTER
Fully digital clock frequency doubler
2010 Volume 7 Issue 6 Pages 416-420
Details
2010 Volume 7 Issue 6 Pages 416-420
This paper presents a clock frequency doubler, having the function of automatic adjustable duty cycle without feedback loops. The duty cycle amount can be automatically adjustable using digitized delay block and a counter. This simplifies the design structure and allows the circuit to operate over a wide range of input frequency variation. The simulation results show that this frequency doubler operates at a very wide variable input frequency ranging from 650MHz to 1.25GHz.
