A low cost test pattern generator for test-per-clock BIST scheme

Shaochong Lei; Zhen Wang; Zeye Liu; Feng Liang

doi:10.1587/elex.7.672

LETTER

A low cost test pattern generator for test-per-clock BIST scheme

Shaochong Lei, Zhen Wang, Zeye Liu, Feng Liang

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Keywords: Built-in self-test, test-per-clock, test pattern generation, single input change, low power

JOURNAL FREE ACCESS

2010 Volume 7 Issue 10 Pages 672-677

DOI https://doi.org/10.1587/elex.7.672

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Abstract

Test power and test overhead are crucial to VLSI and SOC testing. This paper proposes a low cost test pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme. The proposed method utilizes a two-dimensional TPG and a bit-XOR array to reduce area overhead, and generates single input change (SIC) sequences to reduce input transitions of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can achieve high fault coverage and effectively reduce test power.

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