A 8bit two stage time-to-digital converter using time difference amplifier

Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada

doi:10.1587/elex.7.943

LETTER

A 8bit two stage time-to-digital converter using time difference amplifier

Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada

Author information

Keywords: time-to-digital converter, TDC, time difference amplifier

JOURNAL FREE ACCESS

2010 Volume 7 Issue 13 Pages 943-948

DOI https://doi.org/10.1587/elex.7.943

Details

Abstract

We propose a 8bit two stage time-to-digital converter (TDC) using a time difference amplifier. The time resolution is 1.89ps, and DNL of 0.9 and INL of 1.0 are achieved in simulation assuming the standard 0.18um CMOS. To amplify the time residue of the first stage, the 16x cascaded time difference amplifier (TDA) using differential logic delay cells is employed. Time resolution of the proposed TDC becomes finer by employing the 16x cascaded TDA and the linearity is improved by using only one TDA in the two stage TDC instead of using a lot of TDAs.

Corresponding author

Register with J-STAGE for free!