IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology
Ching-Che ChungDuo ShengSung-En Shen
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JOURNAL FREE ACCESS

2011 Volume 8 Issue 15 Pages 1245-1251

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Abstract

A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper. The proposed ADDCC can correct the duty-cycle error of the input clock to 50% duty-cycle. The acceptable duty-cycle range and frequency range of input clock is from 20% to 80% and from 250MHz to 1GHz, respectively. The proposed ADDCC is implemented on a standard performance 65nm CMOS process, and the power consumption is 1.52mW at 250MHz and 5.83mW at 1GHz, respectively.

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© 2011 by The Institute of Electronics, Information and Communication Engineers
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