IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Efficiency optimization of charge pump circuit in NAND FLASH memory
SungWook ChoiDuckJu KimJunSeob ChungBongSeok HanJeaGun Park
Author information
JOURNAL FREE ACCESS

2011 Volume 8 Issue 16 Pages 1343-1347

Details
Abstract

In this paper, power efficiency optimization scheme of charge pump circuit in NAND FLASH memory was proposed. The proposed scheme was implemented in program/erase charge pump by pump stage number control method. The maximum power efficiency of this pump is about 30%, and the maximum point is around 70% point of highest voltage level. So in this paper, to operate program/erase pump in highest power efficiency area, the pump stage number control scheme is proposed and evaluated in 20nm 64Gb MLC NAND FLASH memory circuit. Simulation result shows overall improvement of power efficiency, and at the wafer test about 10mA peak current reduction and overall improvement of power dissipation are found.

Content from these authors
© 2011 by The Institute of Electronics, Information and Communication Engineers
Previous article Next article
feedback
Top