Power consumption and Static noise margin (SNM) are most important parameters for memory design. The main source of power consumption in SRAM cell is due to large voltage swing on the bitlines during write operation. To reduce the power consumption and enhance the performance of the SRAM cell, we propose a Low-power fast (LPF) SRAM cell. The cell is simulated in terms of power, delay and read stability. The simulated result shows that the read and write power of the proposed cell is reduced up to 33% and 57.12% at 1.2V (in CMOS 0.12µm technology) respectively compared to the 6T cell. The read SNM of the LPF cell is 2x times of the conventional cell.