An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

Arash Abadian; Mojtaba Lotfizad; M.B. Ghaznavi-Ghoushchi; Nasser Erfani Majd

doi:10.1587/elex.8.1801

LETTER

An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

Arash Abadian, Mojtaba Lotfizad, M.B. Ghaznavi-Ghoushchi, Nasser Erfani Majd

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Keywords: all digital phase locked-loop, digitally controlled oscillator, glitch removal, low power, low complexity

JOURNAL FREE ACCESS

2011 Volume 8 Issue 21 Pages 1801-1807

DOI https://doi.org/10.1587/elex.8.1801

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Abstract

In this letter, a new all digital phase locked loop (ADPLL) is proposed. The proposed ADPLL is introduced a new locking procedure with low complexity which results in an ultra low power design. The design uses only two up-down counters for finding the reference frequency. An efficient glitch removal filter and a new low power DCO are also introduced in this letter. The DCO achieves a reasonably high resolution of 1ps. The power consumption of the proposed ADPLL at 500MHz frequency is 820µW. The proposed ADPLL is simulated in 180nm CMOS with Hspice and verified by MATLAB.

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