VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In this paper, we parallelize the Pathfinder global routing algorithm -a widely used FPGA routing algorithm- for running on multi-core systems to improve runtime of routing process. Our experimental results show that the runtime of proposed multi-threaded global routing reduces by 47.8% and 70.9% (on average) with 2 and 4 concurrent threads, respectively on a quad-core processor without any quality degradation.