Work function modulation of PtSi by alloying with Yb to achieve ultra-low contact resistance for advanced CMOS was investigated. Pt_xYb_ySi was formed by depositing Pt(6-18nm)/Yb(2-14nm)/n-Si(100) stacked structure followed by 400-800°C/1-30min silicidation in N₂ ambient. It was found that barrier height for electron(Φ_Bn) was decreased as the silicidation temperature and time increased, and Φ_Bn was reduced to 0.52eV by depositing Pt(6nm)/Yb(14nm) followed by 800°C/30min silicidation. It was found that Yb diffusion toword the silicide/Si interface was enhanced, compared to the sample formed by 500-600°C silicidation, which leads to further decrease of Φ_Bn. The estimated effective work function of PtSi decreased from 4.92eV to 4.57eV.