LETTER
Fully parallel comparator for the moduli set {2n,2n-1,2n+1}
2011 Volume 8 Issue 12 Pages 897-901
Details
2011 Volume 8 Issue 12 Pages 897-901
A novel circuit based on sign detection is introduced in this paper which uses the subtraction for comparing two numbers without carrying out a full comparison and conversion. Thus, the proposed schema decreases the delay significantly using only a little redundant hardware in contrast to previous works. Also the time complexity of the new design has the best results comparing to the previous work.
