LETTER
Model of Network-on-Chip routers and performance analysis
2011 Volume 8 Issue 13 Pages 986-993
Details
2011 Volume 8 Issue 13 Pages 986-993
This paper presents a generic analytical performance model of Network-on-Chip (NoC) router, which is further used to analyze the performance of a whole wormhole NoC. We focus on the analysis of various packet blocking-conditions at the router input-queues for a more accurate estimation of waiting time. Based on this estimation, some key performance metrics of NoC, such as the buffer utilization and packet transfer latency, are both computed. Compared with some previous model, it presents more accurate results: for buffer utilization ratio, the error is 6.30%; for packet transfer latency, it is about 5.98%.
