A parasitic insensitive C-DAC with time-mode reference voltage generator
2012 Volume 9 Issue 8 Pages 745-751
Details
2012 Volume 9 Issue 8 Pages 745-751
This paper proposes a 10-bit parasitic insensitive capacitive DAC with time-mode reference voltage generator for high resolution LCD drivers. In this architecture, the parasitic insensitive operation is achieved by modifying the switch control scheme of the DAC. Furthermore, the time-mode reference voltage generator replaces the conventional resistor divider scheme, which reduces the size of the reference generation circuitry and enables programmable DAC reference voltage. The proposed DAC was designed with CMOS 0.35µm technology. The maximum INL and DNL showed -0.049LSB and -0.026LSB even with 10% parasitic capacitance.
