The metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) using the (Bi,La)₄Ti₃O₁₂ (BLT) as a ferroelectric and SrTa₂O₆ (STA) as a buffer layer is prepared. The Au/STA/Si structure shows about 1 nF/cm² of the accumulation capacitance value which is equivalent to about 6.2 nm of SiO₂. The leakage current density is lower than 10⁷ A/cm² under 5 V. The remanent polarization of the 420 nm-thick BLT film was 35.2 μC/cm² at 450 kV/cm. The MFMIS-FET was fabricated with different area ratio (A_I/A_F) from 1 to 8. From the drain current-gate voltage characteristics at the drain voltage of 0.2 V, the memory window is only 0.5 V for the device with A_I/A_F = 1 but it is increased to 1.8 V as the A_I/A_F is increased to 8. For the A_I/A_F ratio of 8, the "on" state of the drain current of 1.12 × 10^-5 A rapidly drops after 10⁵ s to 2 × 10^-6 A and the "off" state current increase from 10^-7 A to 10^-6 A after 10⁵ s. The on/off current ratio decrease from 3 × 10² to 8.